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?2008 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
SG6901A " Rev. 1.0.2
18
Physical Dimensions
0.10
C
C
A
SEE DETAIL A
NOTES: UNLESS OTHERWISE SPECIFIED
  A) THIS PACKAGE CONFORMS TO JEDEC
  MS-013, VARIATION AC, ISSUE E
  B) ALL DIMENSIONS ARE IN MILLIMETERS.
  C) DIMENSIONS DO NOT INCLUDE MOLD
  FLASH OR BURRS.
  E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
PIN ONE
INDICATOR
0.25
1
10
B
C    A
M
20
11
B
X 45?/DIV>
8?/DIV>
0?/DIV>
SEATING PLANE
GAGE PLANE
DETAIL A
SCALE: 2:1
SEATING PLANE
LAND PATTERN RECOMMENDATION
  F) DRAWING FILENAME: MKT-M20BREV3
0.65
1.27
2.25
9.50
13.00
12.60
11.43
7.60
7.40
10.65
10.00
0.51
0.35
1.27
2.65 MAX
0.30
0.10
0.33
0.20
0.75
0.25
(R0.10)
(R0.10)
1.27
0.40
(1.40)
0.25
D) CONFORMS TO ASME Y14.5M-1994
 
 
Figure 31. 20-Pin Small Outline Integrated Circuit (SOIC)
 
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchilds worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
 
Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
.
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